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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9051 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., 10-bit, 60 msps a/d converter functional block diagram encode AD9051 t/h sum amp dac adc 5v decode logic timing ain ainb 5v gnd reference circuits 10 bwsel adc in out features 60 msps sampling rate 9.3 effective number of bits at f in = 10.3 mhz 250 mw total power at 60 msps selectable input bandwidth of 50 mhz or 130 mhz on-chip t/h and voltage reference single 5 v supply voltage 5 v or 3 v logic i/o compatible input range and output coding options available applications medical imaging digital communications professional video instrumentation set-top box general description the AD9051 is a complete 10-bit monolithic sampling analog- to-digital converter (adc) with an onboard track-and-hold and reference. the unit is designed for low cost, high performance applications and requires only 5 v and an encode clock to achieve 60 msps sample rates with 10-bit resolution. the encode clock is ttl compatible and the digital outputs are cmos; both can operate with 5 v/3 v logic. the two-step architecture used in the AD9051 is optimized to provide the best dynamic performance available while maintaining low power consumption. a 2.5 v reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. fabricated on a state-of-the-art bicmos process, the AD9051 is packaged in a space saving surface mount package (ssop) and is specified over the industrial tem- perature range (C40 c to +85 c). 2010 781/461-3113 c
AD9051brs/ AD9051brsz AD9051brs-2v/ AD9051brsz-2v 8.76 9.3 9.0 8.8 56.5 56 54 55.5 56.5 55 9.1 8.8 8.6 56.5 55 53 56.5 55.5 54 53.5 54.5 8.59 52.5 53.5 rev. c
AD9051brs/ AD9051brsz AD9051brs-2v/ AD9051brsz-2v rev. c
rev. AD9051 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9051 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v analog inputs . . . . . . . . . . . . . . . . . . . . C0.5 v to v d + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d vref input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . . 150 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range. table i. digital coding (single-ended input with ain, ainb bypassed to gnd) or digital output analog input voltage level (out of range) ms b... lsb 3.126 (3.50) * positive full scale + 1 lsb 1 1111111111 2.5 midscale 0 0111111111 1.874 (1.50) * negative full scale C 1 lsb 1 0000000000 * (brs-2v version) c
rev. C5C AD9051 pin function descriptions pin no. mnemonic description 1, 6, 7, 12, 21, 23 gnd ground 2, 8, 11 v d analog 5 v power supply 3 vrefout internal bandgap voltage reference (nominally 2.5 v) 4 vrefin input to reference amplifier. voltage reference for adc is connected here. 5 bwsel bandwidth select. nc = 130 mhz nominal. +v d = 50 mhz nominal. 9 ainb complementary analog input pin (analog input bar) 10 ain analog input pin 13 encode encode clock input to adc. internal t/h is placed in hold mode (adc is encoding) on rising edge of encode signal. 14 or out of range signal. logic 0 when analog input is in nominal range. logic 1 when analog input is out of nominal range. 15 d9 (msb) most significant bit of adc output 16C19 d8Cd5 digital output bits of adc 20, 22 v dd digital output power supply (only used by digital outputs) 24C27 d4Cd1 digital output bits of adc 28 d0 (lsb) least significant bit of adc output pin configuration 14 13 12 11 10 9 8 1 2 3 4 7 6 5 17 16 20 28 27 26 25 24 23 22 21 19 18 15 top view (not to scale) AD9051 gnd d3 d2 d1 d0 (lsb) v d vrefout vrefin v dd gnd d4 bwsel gnd gnd v d ainb ain d5 v dd gnd v d gnd encode or d6 d9 (msb) d8 d7 n n + 1 n + 2 n + 3 n + 4 n + 5 ain encode digital outputs t a t eh t el t pd n ?5 n ?4 n 3 n 2 n ?1 n figure 1. timing diagram 12k 12k 12k 12k ainb (pin 9) ain (pin 10) input buffer v d v dd (pins 20, 22) +3v to +5v d0 d9, or v d encode (pin 13) v d vref out (pin 3) figure 2. equivalent circuits analog input encode output stage vref c
rev. AD9051 C6C clock rate msps 255 15 dissipation mw 15 250 245 240 235 230 225 220 215 210 20 25 30 35 40 45 50 55 60 tpc 1. power dissipation vs. clock rate frequency mhz 60 50 0 90 10 snr/sinad db 20 30 40 50 60 70 80 59 55 53 52 51 58 57 54 56 snr @ 40msps sinad @ 40msps sinad @ 60msps snr @ 60msps tpc 2. snr/sinad vs. ain frequency frequency mhz 50 100 0 90 10 db 20 30 40 50 60 70 80 55 75 85 90 95 60 65 80 70 2nd @ 40msps 2nd @ 60msps 3rd @ 60msps 3rd @ 40msps tpc 3. harmonics vs. ain frequency analog input frequency mhz 0 1 adc gain db 1 4 6 201 3 5 2 40 52 80 118 141 bwsel enabled bwsel disabled tpc 4. adc gain vs. ain frequency temperature c 59 40 snr db 57.5 56 55 65 encode = 40msps 56.5 55.5 57 45 25 0 20 encode = 60msps 85 58.5 58 ain = 10.3mhz tpc 5. snr vs. temperature encode msps 60 5 snr db 59 56 50 70 57 51 58 40 30 20 10 55 52 53 54 50 60 ain = 10.3mhz tpc 6. snr vs. clock rate c
rev. AD9051 C7C frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain = 10.3mhz encode = 40msps snr = 58.6db sinad = 57.69db 0 2.5 5.0 7.5 10 12.5 15 17.5 20 tpc 7. fft plot 40 msps, 10.3 mhz frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain = 15.2mhz encode = 40msps snr = 58.47db sinad = 57.04db 0 2.5 5.0 7.5 10 12.5 15 17.5 20 tpc 8. fft plot 40 msps, 15.2 mhz frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain = 10.3mhz encode = 60msps snr = 58.15db sinad = 57.25db 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 tpc 9. fft plot 60 msps, 10.3 mhz frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain = 15.2mhz encode = 60msps snr = 58.29db sinad = 57.23db 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 tpc 10. fft plot 60 msps, 15.2 mhz frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain = 21.7mhz encode = 60msps snr = 57.76db sinad = 56.27db 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 tpc 11. fft plot 60 msps, 21.7 mhz frequency mhz 0 10 40 100 30 90 20 50 80 70 60 db ain1 = 9.5mhz, 7dbfs ain2 = 9.9mhz, 7dbfs imd = 65dbc encode = 60msps 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 tpc 12. two-tone imd c
rev. AD9051 C8C encode msps 1.2 0 0 60 10 % gain error 20 30 40 50 1.0 0.8 0.6 0.4 0.2 tpc 13. gain vs. clock rate encode msps 16 0 0 60 10 offset mv 20 30 40 50 14 12 10 8 6 4 2 tpc 14. offset vs. clock rate duty cycle % 60 40 25 55 30 snr db 35 40 45 50 58 56 54 52 50 48 46 60 65 70 75 44 42 snr @ 40msps snr @ 60msps tpc 15. snr vs. duty cycle temperature c 6.5 40 t pd ns 5 4 65 3v falling 4.5 45 25 0 20 3v rising 85 6 5.5 5v falling 5v rising tpc 16. t pd vs. temperature 3 v/5 v source current ma 2.51 ref voltage 2.50 2.44 2.42 2.45 2.43 2.46 v out 2.47 2.48 2.49 0.1 0.25 0.4 0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0 tpc 17. reference load regulation code 80 % occurrance 20 0 30 10 40 50 60 70 512 513 514 515 516 517 518 tpc 18. midscale histogram (inputs tied) c
rev. AD9051 C9C theory of operation refer to the block diagram on the front page. the AD9051 employs a subranging architecture with digital error correction. this combination of design techniques ensures true 10-bit accuracy at the digital outputs of the converter. at the input, the analog signal is buffered by a high speed differ ential buffer and applied to a track-and-hold (t/h) that holds the analog value present when the unit is strobed with an encode command. the conversion process begins on the rising edge of this pulse. the two stage architecture completes a coarse and then a fine conversion of the t/h output signal. error correction and decode logic correct and align data from the two conversions and present the result as a 10-bit parallel digital word. output data are strobed on the rising edge of the encode command. the subranging architecture results in five pipeline delays for the output data. refer to the AD9051 timing diagram. using the AD9051 3 v system the digital input and outputs of the AD9051 can be easily configured to directly interface to 3 v logic systems. the encode input (pin 13) is ttl compatible with a logic threshold of 1.5 v. this input is actually a cmos stage (refer to equivalent encode input stage) with a ttl threshold, allowing operation with ttl, cmos and 3 v cmos logic families. using 3 v cmos logic allows the user to drive the encode directly without the need to translate to 5 v. this saves the user power and board space. as with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. the AD9051 outputs can also directly interface to 3 v logic systems. the digital outputs are standard cmos stages (refer to AD9051 output stage) with isolated supply pins (pins 20, 22 v dd ). by varying the voltage on the v dd pins, the digital output levels vary respectively. by connecting pins 20 and 22 to the 3 v logic supply, the AD9051 will supply 3 v output levels. c are should be taken to filter and isolate the output supply of the AD9051 as noise could be coupled into the adc, lim iting performance. analog input the analog input of the AD9051 is a differential input buffer (refer to AD9051 equivalent analog input). the differential inputs are internally biased at 2.5 v, obviating the need for external biasing. excellent performance is achieved whether the analog inputs are driven single-endedly or differentially (for best dynamic performance, impedances at ain and ainb should match). figure 3 shows typical connections for the analog inputs when using the AD9051 in a dc-coupled system with single-ended signals. all components are powered from a single 5 v supply. the ad820 is used to offset the ground referenced input signal to the level required by the AD9051. ac coupling of the analog inputs of the AD9051 is easily accomplished. figure 4 shows capacitive coupling of a single- ended signal while figure 5 shows transformer coupling differ entially into the AD9051. v in 0.625v to +0.625v 5v ad9631 140 140 5v AD9051 9 10 5v 1k ad820 1k 0.1 f 0.1 f figure 3. single supply, single-ended, dc-coupled AD9051 +5v ad9631 140 140 5v AD9051 9 10 5v 0.1 f 0.1 f v in 0.625v to +0.625v figure 4. single-ended, capacitively-coupled AD9051 +5v 5v 9 10 5v 0.1 f AD9051 t1-1t 50 v in 0.625v to +0.625v ad9631 140 140 figure 5. differentially driven AD9051 using trans- former coupling the ad830 provides a unique method of providing dc level shift for the analog input. using the ad830 allows a great deal of flexibility for adjusting offset and gain. figure 6 shows the ad830 configured to drive the AD9051. the offset is provided by the internal biasing of the AD9051 differential input (pin 9). for more information regarding the ad830, see the ad830 data sheet. 1 2 3 4 ad830 +15v 5v 7 10 9 0.1 f +5v AD9051 v in 0.625v to +0.625v figure 6. level-shifting with the ad830 c
rev. AD9051 C10C overdrive of the analog input special care was taken in the design of the analog input section of the AD9051 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 1.875 v to 3.125 v (1.25 v p-p centered at 2.5 v). out-of-range compara- tors detect when the analog input signal is out of this range and the input buffer is clamped. the digital outputs are locked at their maximum or minimum value (i.e., all 0 or all 1). this precludes the digital outputs changing to an invalid value when the analog input is out of range. the input is protected to one volt outside the power supply rails. for nominal power (5 v and ground), the analog input will not be damaged with signals from +5.5 v to C0.5 v. timing the performance of the AD9051 is very insensitive to the duty cycle of the clock. pulsewidth variations of as much as 15% for encode rates of 40 msps and 10% for encode rates of 60 msps will cause no degradation in performance. (see figure 17, snr vs. duty cycle.) the AD9051 provides latched data outputs, with five pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (refer to figure 1, timing diagram). the length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the AD9051; these transients can detract from the converters dynamic performance. power dissipation the power dissipation specification in the parameter table is measured under the following conditions: encode is 60 msps, analog input is Cfs. as shown in figure 3, the actual power dissipation varies based on these conditions. for instance, reducing the clock rate will reduce power as expected for cmos-type devices. the loading determines the power dissipated in the output stages. the analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. power dissipation increases as more data bits switch at faster rates. for instance, if the input is a dc signal that is out of range, no output bits will switch. this minimizes power in the output stages, but is not realistic from a usage standpoint. the dissipation in the output stages can be minimized by inter- facing the outputs to 3 v logic (refer to using the AD9051, 3 v system). the lower output swings minimize power consumption as follows: (1/2 c load v dd 2 update rate). voltage reference a stable and accurate 2.5 v voltage reference is built into the AD9051 (pin 3, vrefout). in normal operation the internal reference is used by strapping together pins 3 and 4 of the AD9051. the internal reference has 500 a of extra drive cur- rent that can be used for other circuits. some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9051, which cannot be obtained by using the internal refer- ence. for these applications, an external 2.5 v reference can be used to connect to pin 4 of the AD9051. the vrefin requires 2 a of drive current. the input range can be adjusted by varying the reference voltage applied to the AD9051. no appreciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly. c
AD9051 rev. c C11C outline dimensions compliant to jedec standards mo-150-ah 060106-a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 7.28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9051brs ?40c to +85c 28-lead shrink small outline package (ssop) rs-28 AD9051brs-2v ?40c to +85c 28-lead shrink small outline package (ssop) rs-28 AD9051brsrl ?40c to +85c 28-lead shrink small outline package (ssop) rs-28 AD9051brsz ?40c to +85c 28-lead shrink small outline package (ssop) rs-28 AD9051brszrl ?40c to +85c 28-lead shrink small outline package (ssop) rs-28 AD9051brsrl-2v ?40c to +85c 28-lead shri nk small outline package (ssop) rs-28 AD9051brsz-2v ?40c to +85c 28-lead shri nk small outline package (ssop) rs-28 AD9051brszrl-2v ?40c to +85c 28-lead shri nk small outline package (ssop) rs-28 1 z = rohs compliant part. revision history 11/10rev. b to rev. c changes to specifications section ................................................... 2 deleted evaluation board section ................................................ 10 updated outline dimensions ........................................................ 11 changes to ordering guide ........................................................... 11 7/01rev. a to rev. b edits to absolute maximum ratings ............................... 4 ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00558-0-11/10(c)

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